The Wishbone bus is an open source hardware computer bus specification intended to let different logic blocks within an integrated circuit communicate with each other. This talk will introduce a set of memory mapped data structures that allow designers to describe their own logic blocks, thus allowing for the auto-discovery of devices on a Wishbone bus.
The Wishbone bus is an open source hardware computer bus intended to let different logic blocks within an integrated circuit communicate with each other. This talk will introduce a set of memory mapped data structures that allow designers to describe their own logic blocks. Thus, for compliant chip designs, the operating system can enumerate the Wishbone bus inside the integrated circuits and load the appropriate drivers, similar to PCI or USB. The proposed specification is already being used in a set of FPGA based cards being developed at the Open Hardware Repository. By defining a new bus type within the Linux kernel, the driver for each board can register as a Wishbone controller and benefit from automatic enumeration. The bus controller can use the information it retrieves to load or activate the appropriate set of drivers to manage either the whole board or the various peripherals that are attached to the internal Wishbone bus. Such a scheme greatly simplifies managing the variety of FPGA binary images, by allowing automatic division of the problem space. Even when a single driver is needed for the whole device-set within the internal bus, a standardized identification mechanism reliefs system administrators from manually matching FPGA images and software drivers.
Speakers: Manohar Vanga