The coreboot ramstage was created because Linux could not correctly a PCI bus in 1999. Since then, the ramstage has grown in complexity and, in conjunction with depth charge, is well on the way to becoming a small kernel. At the 2018 OSFC Minnich[?] suggested that we might consider making the ramstage optional, since he had found that some im some ports (RISCV) and some situations (linuxboot) it was no longer needed, and it was a significant burden in terms of boot speed and code. Intel and Google have been studying this idea. In this talk we discuss our exploration into making the ramstage optional. There is a significant boot time performance improvement.
Speakers: ronald g. minnich Tan Lean Sheng