Using LLVM on a new CPU or a new platform may require changes to the internal assembler. A common use case is the support of new instructions for a new CPU. In this talk I show how to add a complete new CPU feature, using the MIPS Octeon variant as an example.
LLVM has an integrated assembler in the MC layer. If a CPU vendor adds new instructions then it is necessary to extend the instruction description in order to use the new instructions at least in inline assembly. It would be even better if these instructions are also considered by the code generation. In this talk I show how to add a new CPU feature, new instructions and instruction aliases. I also demonstrate how the new instructions are selected by the code generation. As example I use the Octeon instructions which I added to the MIPS backend for the LLVM 3.5 release.
Speakers: Kai Nacke