Joshua Mack

Heterogeneous architectures, composed of a pool of general-purpose processors and accelerators, on one hand offers the ability to balance the application performance, programming flexibility, and energy consumption. On the other hand, they give rise to a number of challenges on a) designing and implementing a suitable architecture for the needs of the target applications, b) deploying dynamic and low-overhead resource management strategies, and c) effectively enabling execution of pipelined workflows for streaming applications. Furthermore, application developers need productive tools to port their software-defined radio applications to increasingly heterogeneous SoCs. We think that application developers should not waste their time reading datasheets or APIs for SoC-specific kernel extensions just to take full advantage of their hardware. With these in mind, this talk will discuss strategies we are using to address the aforementioned inter-related challenges through our vertically integrated compile-time and run-time environment CEDR: a Compiler-integrated, Extensible, DSSoC Runtime.

CEDR is an open-source ecosystem that runs in Linux user-space and enables compilation and development of user applications, resource management strategies, and accelerator integration in one unified framework. CEDR supports highly recurring, stream-based application graphs through pipelined execution and processing element based work queues. CEDR is built on a thread-per-PE scheduling methodology, enables integration of complex resource management heuristics that rely on work queues and require reservation-based policies. CEDR supports contemporary scheduling algorithms built on imitation learning (IL) that uses complex schedulers offline to construct an Oracle and effortlessly replicates those decisions online using machine learning models such as regression trees and neural networks. We will demonstrate CEDR deployed on the Zynq UltraScale MPSoC by conducting execution time, throughput, resource utilization analysis through dynamically arriving workload scenarios composed of Radar and WiFi applications. We will demonstrate the distinct plug-and-play integration points offered by CEDR for application engineers and hardware architects through case studies that illustrate our ability to rapidly evaluate various configurations of applications, schedulers, and accelerator IPs.

Historically, programming heterogeneous systems has been quite a challenge. While programming support for basic general-purpose accelerators such as GPUs has become quite mature in many ways, general heterogeneous SoCs in particular can feature a much broader range of accelerators in their efforts to minimize power consumption while maximizing performance. Many SoCs, though, are designed with accelerators tailored for the domain -- such as signal processing -- in which they’ll be used: Domain-Specific SoCs. As SoC platforms become ever-more heterogeneous, we think that application developers shouldn’t need to waste time reading datasheets or APIs for SoC-specific kernel extensions just to take full advantage of their hardware. With this in mind, in this talk we will discuss strategies we are using to automate mapping of LLVM-compatible languages to heterogeneous platforms with no intervention (not even #pragmas) from the programmer.

To this end, we present our prototype of a software stack that seeks to address both of these needs. To meet the first need, we developed an LLVM-based hybrid compile/run-time toolchain to extract the semantic operations being performed in a given application. With these semantic operations extracted, we can link in additional libraries that enable dispatch of certain kernels (such as a Fast Fourier Transform) to accelerators on the SoC without user intervention. To evaluate the functionality of this toolchain, we developed a runtime system built on top of QEMU+Linux that includes scheduling and task dispatch capabilities targeting hypothetical SoC configurations. This enables behavioral modeling of these accelerators before silicon (or even FPGA) implementations are available. The focus here will be on the LLVM-mapping aspects, but a brief overview of our SoC simulation environment will be presented as well.