Pavel Pisa

👥 1 conference
🎤 1 talk
📅 Years active: 2023 to 2023

Biography

He studied cybernetics and robotics at CTU FEE, where he currently teaches and works on projects using GNU/Linux and other processor technologies. He participates in design of firmware and electronics of laboratory and medical devices and precise servo control in PiKRON.com company. He provides consultations to more companies in the field as well.
The list of some open-source projects contributions https://www.openhub.net/accounts/ppisa
Open Technologies Research Education and Exchange Services https://gitlab.fel.cvut.cz/otrees/org/-/wikis/knowbase
CAN bus related project at FEE CTU http://canbus.pages.fel.cvut.cz/
Notices mainly to organize own thoughts how to pass and share knowledge with others https://www.abclinuxu.cz/blog/logic
— biography from FOSDEM 2023
https://archive.fosdem.org/2023/schedule/speaker/pavel_pisa/

Conferences

1 known conferences

👥 FOSDEM 2023 📅 04 Feb 2023

🎤 QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming
05 Feb 2023 show details

QtRvSim is a graphical RISC-V microprocessor simulator developed to aid computer architecture understanding. It is designed to cover the track of an undergraduate course based on the book "Computer Organization and Design" by Patterson and Hennessy. The class can begin with a single-cycle microarchitecture and gradually add more complex features like pipeline, hazard unit (with or without forward paths), configurable data and instruction cache, emulation of basic system calls, and finally, memory-mapped peripherals. The simulator provides an editor with an integrated assembler. The online version and course materials are available at https://comparch.edu.cvut.cz/, configurable data and instruction cache, emulation of basic system calls, and finally, memory-mapped peripherals. The simulator provides an editor with an integrated assembler. The online version and course materials are available at [QtRvSim is a graphical RISC-V microprocessor simulator developed to aid computer architecture understanding. It is designed to cover the track of an undergraduate course based on the book "Computer Organization and Design" by Patterson and Hennessy. The class can begin with a single-cycle microarchitecture and gradually add more complex features like pipeline, hazard unit (with or without forward paths), configurable data and instruction cache, emulation of basic system calls, and finally, memory-mapped peripherals. The simulator provides an editor with an integrated assembler. The online version and related course materials are available at comparch.edu.cvut.cz.

The simulator is cycle-accurate (memory operations finish within one cycle), compliant with official RISC-V tests, and supports RV32IM, RV64IM (CLI-only), and Zicsr. Featured peripherals are LEDs, knobs with buttons, a terminal, and an LCD display. It is available for Linux, Windows, macOS, and WebAssembly and is developed on GitHub. Many course materials, recordings, and edited lecture videos are also freely available at comparch.edu.cvut.cz. Czech Technical University in Prague, Technical University in Graz, and the University of Colorado at Colorado Springs are currently employing QtRVSim in their classes. Our previous MIPS edition (QtMips) is used by the National and Kapodistrian University of Athens and Charles University in Prague.

Other people: Jakub Dupak