Babar Khan

FPGAs are increasingly being used in today's embedded systems. But they are notoriously complex for having a difficult programming model. In order to counter this complexity, there has been a growing focus to design FPGA hardware at a higher level of abstraction with new languages and compilers. This talk will serve as "one stop shop" for topics related to these developments.

Are you an embedded developer? Do you like FPGAs? Do you want to know the best programming practices for embedded systems that deploy FPGAs? Do you like economical hardware? Do you like open source projects? If your answer is "yes" to either of the aforementioned questions, then this talk is for you. As the title goes, this talk and its content will actually be "one stop shop" for best practices related to FPGA programming. Considering C-based languages still dominate the embedded systems, the talk will focus on new methodologies that can be broadly implemented while using all C-based (C/C++/C#) languages when it comes to implement your designs on FPGAs. To take it further, the talk will shift focus on C++ as C++ is finally picking up pace to come even more closer to low level hardware as compared to previous C++ standards. The last four C++ standards have come a long way to make C++ language even more compatible with embedded systems. Many open source FPGA libraries are based on modern C++. At the end of the day, you will know how a modern embedded developer can adopt certain coding practices to fully exploit the underlying spatial parallelism of FPGA hardware. Additionally, you will learn about open source compilers, open source projects, and economical FPGAs hardware to implement these best practices.

Although Linux is still the best preferred operating system, the talk begins with a problem statement regarding the dependencies of ANTLR and LLVM on Windows. To this end, the presenter will explain how these dependency issues can be resolved through an easy-to-use environment for building, installing and running native LLVM and ANTLR on Windows. Furthermore, the talk will briefly explain how we can design domain specific languages (DSLs) using a powerful combination of ANTLR and LLVM front end while maintaining a logical isolation of parsing and code generation.

Hardware accelerators are being increasingly integrated into today’s heterogenous computing systems to achieve improved performance. However, the resulting heterogenous hardware also increases the challenge to ensure the security of these accelerators. High-Level Synthesis (HLS) automates the creation of a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). In this talk, I would like to discuss different extensions and methodologies to High-Level Synthesis (HLS) compilers for generating secure accelerators. Precisely addressing the HLS vulnerabilities like side-channel listed in Common Weakness Enumeration (CWE) list.