Recently proposed domain-specific systems-on-chip (DSSoCs) optimize the architecture, computing resources, and run-time management by exploiting the application characteristics for a given domain. As such, DSSoCs can boost the performance and energy-efficiency of software-defined radio (SDR) applications without degrading their flexibility.
Harvesting the full potential of DSSoCs depends critically on integrating an optimal combination of computing resources and their effective runtime utilization. For this reason, the design space exploration process requires evaluation frameworks to guide the design process. Full-system simulators, such as gem5, can perform instruction-level cycle-accurate simulation. However, this level of detail leads to long execution times and is beyond high-level design space exploration requirements. In contrast, hardware emulation using Field-Programmable Gate Array (FPGA) prototypes are substantially faster. However, they involve significantly higher development effort to implement the target SoC and applications. Given the design complexity, there is a strong need for a simulation environment that enables rapid, high-level, simultaneous exploration of scheduling algorithms and power-thermal management techniques.
To this end, we present DS3, an open-source system-level domain-specific system-on-chip simulation framework that targets SDR applications. DS3 framework enables (1) run-time scheduling algorithm development, (2) dynamic thermal-power management (DTPM) policy design, and (3) rapid design space exploration. DS3 facilitates plug-and-play simulation of scheduling algorithms; it also incorporates built-in heuristics and a constraint programming-based scheduler to provide an upper bound of performance (i.e., optimal schedule for a set of applications and an SoC configuration) for users. Hence, it can be used to develop and evaluate new schedulers that can be integrated into GNU Radio. DS3 also includes power dissipation and thermal models that enable users to design and evaluate new DTPM policies. Furthermore, it features built-in dynamic voltage and frequency scaling (DVFS) governors deployed on commercial SoCs.
In this talk as we discuss the DS3 capabilities, we will present a benchmark application suite with applications from wireless communications and radar processing domains including WiFi TX/RX, low-power single-carrier TX/RX, range detection, and pulse Doppler. We will conclude the talk with design-space exploration studies using these applications.
