Paolo Nenzi

A panel discussion covering subjects related to analog circuit simulation tools. Future Verilog-A efforts will be covered. Panel members include all speakers from the analog simulation session immediately preceding the panel discussion.

Other people: Guilherme Brondani Torri Wladek Grabinski Francesco Lannutti

Ngspice project started in 1999 from the latest implementation of of Berkeley's SPICE3 release. In more than a decade of development it has fixed and upgraded it. Parallel execution of device code has been implemented to reduce simulation time for transient analysis. Two implementations are available: using OpenMP and CUDA. The KLU solver has been implemented to reduce simulation time of large circuits. Verilog-A models can be included at compile time using the ADMS model compiler. This presentation will show an overview on the simulator status focusing on the major improvements over the original SPICE3 code.