A discussion about the current state of FOSS HDL simulation and synthesis tools, and possible paths moving forward.

Other people: Philipp Wagner Tristan Gingold Charles Papon

In this talk, we will provide a brief introduction to the State-of-the-Art of High Level Synthesis for FPGA, utterly dominated by privative & vendor specific solutions but quietly becoming mainstream as algorithm acceleration becomes a must to reach the computational power we need to move system intelligence right to the edge.

As an example of how this can be tackled from a FLOSS approach, we will provide a practical example on how to use HDLMake to merge the FPGA bitstream into the Operating System, handling everything as a single Embedded Linux runtime and providing a convenient abstraction to build & manage production grade Cyber-Physical Systems.

A panel discussion on topics related to digital design and simulation.

Other people: Tristan Gingold Fabrizio Ferrandi Maciej Sumiński Tomasz Wlostowski

FPGA features and resources had dramatically increased in the last years. State-of-the-art devices are now too complex to be tackled by a single individual by using standard HDL tools.

The OHR community hosts and maintains a set of Free/Open high-level FPGA development tools that aims both to increase productivity and to empower resource and knowledge sharing.

This tutorial provides a short introduction & demo for two of the main HDL tools at OHR (HDLMake and Libre-FDATool) and finally introduces some of the hottest trends in high-level FPGA design tools.

This tutorial consist in three different blocks, one for each of the featured tools and a final one is left for conclusion and Q&A.

Featured Tools:

HDLMake:

Hdlmake generates multi-purpose makefiles for HDL projects management. It supports local and remote synthesis, simulation, fetching module dependencies from repositories, creating project for multiple FPGA toolchains... All of this can be done with a makefile command or with Hdlmake directly. It supports modularity, scalability, use of revision control systems and code reuse. Hdlmake is free, open and distributed under the GPL license.

Libre-FDATool:

Libre-FDATool is a Python package aimed at helping in the analysis and design of HDL filters from high-level specifications. This Free/Libre Open Source software supports both VHDL and Verilog code generation and relies on a collection of Free scientific and EDA tools for providing advanced features -- simulation, graphics, debugging, etc.

Conclusions / Beyond HLS:

• State-of-the-Art: new All-programmable SoCs, HLS (High-Level Synthesis) tools for FPGA, HW code accelerators...
• Operating System and HDL as a whole. The gateware part of an hybrid CPU+FPGA system can be handled by the Operating System just as a standard dynamic library. Proof of concept: "meta-spec", Yocto Project support for OHR SPEC (Simple PCI Express FMC Carrier).