Atish Patra

RISC-V boot flow has come a long way since in recent times by leveraging the various opensource boot loaders/firmware projects. This also helped in achieving a well-supported and standard boot flow for RISC-V. As a result, developers can use the same boot loaders to boot Linux on RISC-V as they do in other architectures. Currently, U-Boot is used as the last stage boot loader and OpenSBI as the machine mode run time service provider, but there's more work to be done. A few of such future works includes U-boot SPL support, UEFI boot in RISC-V Linux and booting protocol improvements. This talk will focus on some of these ongoing works which are necessary to declare that RISC-V is truly ready for world domination.

The open RISC-V Instruction Set Architecture (ISA) has been growing for the last few years and the momentum behind it is impressive. That does not mean there are no areas that can be improved. For instance, until recently, a major weakness in the RISC-V software ecosystem was the boot loader support. A well-supported and standard boot flow is required before RISC-V can be a truly competitive alternative to existing mainstream ISAs. By focusing on using common open source projects, RISC-V can follow the same boot flow as other popular ISAs, allowing RISC-V to build on past experiences with booting complex systems on various environments. Although RISC-V is leveraging existing projects as much as possible, RISC-V also needs its own trusted firmware to handle RISC-V specific features such as Supervisor Binary Interface (SBI). SBI allows the operating system to interact with the supervisor execution environment (SEE). This requires a separate but modular open source SBI implementation that provides RISC-V specific run time services. OpenSBI is a BSD-2 licensed project. It is designed in such a way that other open source firmware and bootloaders such as U-Boot, coreboot and EDK2 can easily integrate with OpenSBI and do not require their own separate SBI implementation. This avoids implementation duplication with a common open source SBI implementation. Currently the RISC-V boot process is functional with U-Boot being used as the last stage boot loader and OpenSBI as the machine mode run time service provider. There is also an on-going effort to port U-Boot and coreboot as a first stage boot loader, a step necessary to provide more advanced boot flows including secure boot. This paper will discuss how the RISC-V boot process compares to other ISAs and where the community is heading. This will give developers more insight into how the RISC-V boot process works and how they can contribute to improve the RISC-V

Other people: Alistair Francis

Supervisor Binary Interface (SBI) is one of the most fundamental interfaces in RISC-V eco-system. It allows the operating system to interact with the supervisor execution environment (SEE). The SEE always runs in higher privileged mode than the supervisor OS. It can be a simple bootloader in low-end hardware platform, a hypervisor-provided virtual machine in a high-end server, or simply machine mode software in bare metal systems. An unchecked rapid development of many RISC-V systems could lead to incompatibilities between different systems SEE, preventing the use of a common OS binary image.

The RISC-V ISA has defined SBI to provide a cleaner interface for the supervisor OS which makes virtualization and bring-up of new hardware platforms much easier. In hypervisor extended supervisor (HS) mode, an OS or hypervisor interacts with the machine through the same SBI as an OS normally does from supervisor mode. An HS-mode hypervisor is expected to implement the SBI for its virtualized supervisor (VS) mode guest. The current RISC-V SBI only defines a few mandatory functions such as inter-processor interrupts (IPI) interface, reprogramming timer, serial console, and memory barrier instructions. Many important functionalities such as CPU/system power management are not yet defined due to difficulties in accommodating modifications without breaking backward compatibility with the current interface.

This talk presents the ongoing work to make SBI an extensible yet robust specification. The proposal to extend SBI is based on the foundation policy of RISC-V i.e. modularity and openness. It will always be backward compatible with previous versions including the existing aka legacy version. To achieve that, the focus will be only to develop a Base SBI extension that will contain feature list, version and vendor type queries. Once that is ratified, the future extension such as CPU/system power management, vendor extensions can be developed in parallel. The use cases and calling convention of these extensions will be discussed in details. We will also talk about a reference implementation i.e. OpenSBI for the SBI specification. This project will be licensed under most permissive software license which will allow everybody to reuse the OpenSBI code base in their favorite software eco-system in whatever way choose to do so. This will help in reducing SBI fragmentation in future as well.

In the spirit of the open design nature of RISC-V, the goal of this presentation is to continue the open discussion leading to the formalizing RISC-V SBI specification simplifying both hardware and software designs and doing so, contributing to further development of the RISC-V ecosystem.